MT9V032C12STM【PDF 5/13 页】SENSOR IMAGE VGA MONO CMOS 48LCC

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Preliminary ?

MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor

Pin Descriptions

Table 3:

Pin Descriptions

Only pins D OUT 0 through D OUT 9 may be tri-stated

Pin Number

29

10

Symbol

RSVD

SER_DATAIN_N

Type

Input

Input

Description

Connect to D GND .

Serial data in for stereoscopy (differential negative). Tie to

Notes

1

1k Ω pull-up (to 3.3V) in non-stereoscopy mode.

11

SER_DATAIN_P

Input

Serial data in for stereoscopy (differential positive). Tie to

D GND in non-stereoscopy mode.

8

BYPASS_CLKIN_N

Input

Input bypass shift-CLK (differential negative). Tie to 1K Ω

pull-up (to 3.3V) in non-stereoscopy mode.

9

BYPASS_CLKIN_P

Input

Input bypass shift-CLK (differential positive). Tie to D GND

in non-stereoscopy mode.

23

25

EXPOSURE

SCLK

Input

Input

Rising edge starts exposure in slave mode.

Two-wire serial interface clock. Connect to V DD with 1.5K

resistor even when no other two-wire serial interface

peripheral is attached.

28

30

31

32

33

47

24

OE

S_CTRL_ADR0

S_CTRL_ADR1

RESET#

STANDBY

SYSCLK

S DATA

Input

Input

Input

Input

Input

Input

I/O

D OUT enable pad, active HIGH.

Two-wire serial interface slave address bit 3.

Two-wire serial interface slave address bit 5.

Asynchronous reset. All registers assume defaults.

Shut down sensor operation for power saving.

Master clock (26.6 MHz).

Two-wire serial interface data. Connect to V DD with 1.5K

2

resistor even when no other two-wire serial interface

peripheral is attached.

22

STLN_OUT

I/O

Output in master mode — start line sync to drive slave chip

in-phase; input in slave mode.

26

STFRM_OUT

I/O

Output in master mode — start frame sync to drive a slave

chip in-phase; input in slave mode.

20

21

15

16

17

18

19

27

41

42

43

44

45

46

2

3

4

5

LINE_VALID

FRAME_VALID

D OUT 5

D OUT 6

D OUT 7

D OUT 8

D OUT 9

LED_OUT

D OUT 4

D OUT 3

D OUT 2

D OUT 1

D OUT 0

PIXCLK

SHFT_CLKOUT_N

SHFT_CLKOUT_P

SER_DATAOUT_N

SER_DATAOUT_P

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Asserted when D OUT data is valid.

Asserted when D OUT data is valid.

Parallel pixel data output 5.

Parallel pixel data output 6.

Parallel pixel data output 7.

Parallel pixel data output 8

Parallel pixel data output 9.

LED strobe output.

Parallel pixel data output 4.

Parallel pixel data output 3.

Parallel pixel data output 2.

Parallel pixel data output 1.

Parallel pixel data output 0.

Pixel clock out. D OUT is valid on rising edge of this clock.

Output shift CLK (differential negative).

Output shift CLK (differential positive).

Serial data out (differential negative).

Serial data out (differential positive).

PDF: 09005aef824c9998/Source: 09005aef824c999c

MT9V032_LDS_2.fm - Rev. B 3/07 EN

5

Micron Technology, Inc., reserves the right to change products or specifications without notice.

?2006 Micron Technology, Inc. All rights reserved.

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